Electrochemical deposition processes are well-established in modern integrated circuit fabrication. The movement from aluminum to copper metal lines in the early years of the twenty-first century drove a need for increasingly more sophisticated electrodeposition processes and plating tools. Much of the sophistication evolved in response to the need for ever smaller current carrying lines in device metallization layers. These copper lines are formed by electroplating the metal into very thin, high-aspect ratio trenches and vias in a methodology commonly referred to as “damascene” processing.
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally as wafer level packaging (WLP) and through silicon via (TSV) electrical connection technology. These technologies present their own very significant challenges.
The technologies require electroplating on a significantly larger size scale than damascene applications. Depending on the type and application of the packaging features (e.g. through chip connecting TSV, interconnection redistribution wiring, or chip to board or chip bonding, such as flip-chip pillars), plated features are usually, in current technology, greater than about 2 micrometers and typically 5-100 micrometers (for example, pillars may be about 50 micrometers). For some on-chip structures such as power busses, the feature to be plated may be larger than 100 micrometers. The aspect ratios of the WLP features are typically about 1:1 (height to width) or lower, while TSV structures can have very high aspect ratios (e.g., in the neighborhood of about 20:1).
Given the relatively large amount of material to be deposited, not only feature size, but also plating speed differentiates WLP and TSV applications from damascene applications. For many WLP applications, plating must fill features at a rate of at least about 2 micrometers/minute, and typically at least about 4 micrometers/minute, and for some applications at least about 7 micrometers/minute. At these higher plating rage regimes, efficient mass transfer of metal ions in the electrolyte to the plating surface is important.
Higher plating rates present challenges with respect to uniformity of the electrodeposited layer, that is, plating must be conducted in a highly uniform manner. For various WLP applications, plating must exhibit at most about 5% half range variation radially along the wafer surface (referred to as a within wafer non-uniformity, measured as a single feature type in a die at multiple locations across the wafer's diameter). A similar equally challenging requirement is the uniform deposition (thickness and shape) of various features of either different sizes (e.g. feature diameters) or feature density (e.g. an isolated or imbedded feature in the middle of an array). This performance specification is generally referred to as the within die non-uniformity. Within die non-uniformity is measured as the local variability (e.g. <5% half range) of the various features types as described above versus the average feature height or shape within a given wafer die at that particular die location on the wafer (e.g. at the mid radius, center or edge).
A final challenging requirement is the general control of the within feature shape. A line or pillar can be sloped in either a convex, flat or concave fashion, with a flat profile generally, though not always, preferred. While meeting these challenges, WLP applications must compete with conventional, inexpensive pick and place routing operations. Still further, electrochemical deposition for WLP applications may involve plating various non-copper metals such as lead, tin, silver, nickel, gold, and various alloys of these, some of which include copper.